Jitter Compliance


  • Date: May 7th, 2020
  • Time: 11:00 am EST

As the data rate keeps increasing for SerDes channels, signal integrity becomes more and more important in the design process. Passive channels with good S-parameters (e.g. low insertion loss) can no longer ensure that the signal has good timing or that it will pass the jitter compliance test. The jitter budget is usually defined at a low bit error rate and it is hard for both simulation and measurement to obtain jitter at this low bit rate.

The Eye Diagram tool in CST Studio Suite allows engineers to perform jitter analysis efficiently at the very beginning of SerDes channel design as it integrates important techniques for timing analysis (e.g. equalization, encoding and calculation of data independent jitter) in a user friendly GUI. The statistical method used means that jitter at a very low bit error rate can be quickly and accurately estimated.

With this e-seminar, learn about:

  • The jitter calculation methodology used in simulations and measurements.
  • How to simulate complicated SerDes channels in 3D and perform jitter analysis with the Eye Diagram tool, with the example of a UBS 3.1 Type C connector.

Presented by:

  • Longfei BAI | Solution Consultant, SIMULIA


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